(Invited) Challenges of Graphene Process Integration in CMOS Technology

In this paper we have investigated various steps of graphene device fabrication in a 200 mm wafer Si technology environment. This work has also introduced some of the key process modules which may pave the way to large-scale manufacturing of hybrid graphene-Si components. Although the demonstrated p...

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Veröffentlicht in:	ECS transactions 2019-07, Vol.92 (4), p.201-210
Hauptverfasser:	Lisker, Marco, Lukosius, Mindaugas, Lukose, Rasuole, Wenger, Christian, Mai, Andreas
Format:	Artikel
Sprache:	eng
Online-Zugang:	Volltext
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