(Invited) Challenges of Graphene Process Integration in CMOS Technology

In this paper we have investigated various steps of graphene device fabrication in a 200 mm wafer Si technology environment. This work has also introduced some of the key process modules which may pave the way to large-scale manufacturing of hybrid graphene-Si components. Although the demonstrated process flow requires further improvements to increase device yield and reduce variability the practical relevance is emphasized by the facts that first the proposed processes and materials enable efficient encapsulation and low-resistance metal-graphene contacts and secondly they are compatible with those used in the large-scale fabrication of Si-based ICs. Among the key factors which are limiting the performance and yield of the graphene are uniformity after transfer, process-related contaminations, and poor adhesion/delamination of graphene during various processing steps. In fact, availability of clean and uniform graphene layers on large diameter wafers (200/300 mm) can be considered as a critical prerequisite to further progress in the process integration of graphene devices in Si technology environment.