Study of SiGe Surface Cleaning

SiGe is a promising candidate to replace Si in Fin-shaped and GAA (gate all around) FETs (field-effect transistors) due to its higher carrier mobility. However, the presence of Ge oxide in the interfacial layer (IL) between the SiGe channel and HfO2 causes an increase in interface trap density (DIT) and becomes in considerate as a defect of the device. In this study, the IL formation by a combined wet cleaning process with a subsequent annealing step is investigated by X-ray Photo-electron Spectroscopy (XPS). Finally we will present a process sequence leading up to a Ge-oxide free interlayer.