(Invited) Low Resistance Contacts to Nanoscale Semiconductor Devices

Low Resistance Contacts to Nanoscale Semiconductor Devices Krishna C. Saraswat and Gautam Shine Department of Electrical Engineering, Stanford University, Stanford, CA, 94305 As device scaling continues, parasitic resistance largely dominated by contact resistance, is beginning to limit the device performance. Specific contact resistivity, ρc, of a metal-semiconductor (M/S) contact is dependent on the Schottky barrier height, ΦB, and the electrically active dopant density N at that interface. In M/S contacts the metal Fermi level is pinned at the charge neutrality level, ECNL due to metal induced gap states (MIGS), resulting in fixed electron and hole Schottky barrier heights. High ΦB and low N results in high ρc, eclipsing the promise of intrinsic performance of scaled devices. To obtain low ρc it is essential to reduce ΦB and increase N. In this paper we review the problem caused by Fermi level pinning and various methods to overcome this problem and thus obtain low contact resistance. These methods include heavy doping to reduce barrier thickness, Fermi level depinning with interfacial layers, dipole formation at the interface, and heterostructures for barrier lowering.