Integration of Low Temperature SiGe:B Raised Sources and Drains in p-Type FDSOI Field Effect Transistors

In order to enable 3D sequential CoolCubeTM integration, low temperature epitaxy of raised sources and drains below 500°C is required. However, bad surface preparation and degradation of the epitaxial layer quality are then issues that need to be addressed. In this work, we first study different combinations of thermal, wet and dry surface preparation in order to find an optimum sequence. Then, we present for the first time the integration of SiGe:B raised sources and drains grown at 500°C in p-type FDSOI MOSFETs.