(Invited) Si Nanowire Tunnel FETs for Energy Efficient Nanoelectronics

(Invited) Si Nanowire Tunnel FETs for Energy Efficient Nanoelectronics

Experimental results of strained Si nanowire (NW) TFETs with tri-gate and gate all around (GAA) configurations are presented. Steep tunneling junctions formed by ion implantation into silicide (IIS) and low temperature annealing for dopant segregation allow to achieve subthreshold slope SS

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Veröffentlicht in:ECS transactions 2015-03, Vol.66 (4), p.69-78
Hauptverfasser: Zhao, Qing-Tai, Richter, Simon, Knoll, Lars, Luong, Gia Vinh, Blaeser, Sebastian, Schulte-Braucks, Christian, Schäfer, Anna, Trellenkamp, Stefan, Buca, Dan, Mantl, Siegfried
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Sprache:eng
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Zusammenfassung:Experimental results of strained Si nanowire (NW) TFETs with tri-gate and gate all around (GAA) configurations are presented. Steep tunneling junctions formed by ion implantation into silicide (IIS) and low temperature annealing for dopant segregation allow to achieve subthreshold slope SS
ISSN:1938-5862
1938-6737
DOI:10.1149/06604.0069ecst