Interfacial Layer Engineering Using Thulium Silicate/Germanate for High-k/Metal Gate MOSFETs

Thulium silicate (TmSiO) is considered as high-k interfacial layer in high-k/metal gate stacks, providing advantages in terms of EOT scalability and enhanced inversion layer mobility. In this work, we show that optimized annealing conditions for the TmSiO/HfO2/TiN gate stack provide competitive gate leakage current density, symmetric nFET and pFET threshold voltages, while retaining compatibility with CMOS processing and ~20% higher electron and hole mobility than literature data on optimized SiOx/HfO2 stacks at EOT as low as 0.65 nm. We also evaluate cleaning procedures to facilitate thulium germanate formation on Ge channel materials and found that HF cleaning optimization is needed to allow thulium germanate formation while keeping surface roughness at an acceptable level.