Arsenic Dimer (As 2 + ) Lightly Doped Drain (LDD) Implantation Study for 20nm Logic Device Development

Process variation presents a significant challenge to future scaling of VLSI technology. Junction depth scaling with small Vth variation is required for the 45 nm technology node and beyond. Variations in MOSFET characteristics due to random dopant fluctuation (RDF) may become a fundamental limit to device scaling and circuit complexity. Arsenic dimer (As 2 + ) implant has been used for the formation of ultra-shallow source drain extensions for NMOS transistors below 45nm, CMOS logic process. As Dimer requires only half the dose and twice the energy of equivalent As + so it is more favorable for much lower energy (＜ƒ5KeV) implantation. A comparison of electrical parameters including drive current, Rtotal, junction breakdown voltage, gate to drain overlap capacitance and dopant SMIS profile indicates equivalent process performance for dimer and As + implantation. However, arsenic dimer implantation showed better Vth mismatch performance than conventional As + implantation.