Micro Unetched Oxide Defect during Buffered Oxide Etchant Process
There are two oxide regions, high and low voltage in NAND flash memory devices, in order to improve program speed and reliability. Generally, the two regions are achieved with pattern blocking by using PR(Photo Resistor) followed by etching of low voltage oxide with BOE(Buffered Oxide Etchant). Howe...
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Veröffentlicht in: | ECS transactions 2013-08, Vol.58 (6), p.127-132 |
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description | There are two oxide regions, high and low voltage in NAND flash memory devices, in order to improve program speed and reliability. Generally, the two regions are achieved with pattern blocking by using PR(Photo Resistor) followed by etching of low voltage oxide with BOE(Buffered Oxide Etchant). However, as the 10nm scale NAND flash devices are massively manufactured, 0.2um size defects after oxide etching with BOE are newly detected. Partially unetched oxide defects in low voltage oxide region causes the thicker tunnel oxide and influences abnormal electron's tunneling. As the result, program and erase speed are declined on the relevant transistor, and it causes a yield drop by the electronic characteristics. As possible sources of the defects, the micro impurities in chemical or the micro bubbles from surfactant are suspected, but correct root cause is not yet known. In this study, the effects of filter pore size and nozzle movement of cleaning equipment are examined in other to reduce the defects. |
doi_str_mv | 10.1149/05806.0127ecst |
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Generally, the two regions are achieved with pattern blocking by using PR(Photo Resistor) followed by etching of low voltage oxide with BOE(Buffered Oxide Etchant). However, as the 10nm scale NAND flash devices are massively manufactured, 0.2um size defects after oxide etching with BOE are newly detected. Partially unetched oxide defects in low voltage oxide region causes the thicker tunnel oxide and influences abnormal electron's tunneling. As the result, program and erase speed are declined on the relevant transistor, and it causes a yield drop by the electronic characteristics. As possible sources of the defects, the micro impurities in chemical or the micro bubbles from surfactant are suspected, but correct root cause is not yet known. In this study, the effects of filter pore size and nozzle movement of cleaning equipment are examined in other to reduce the defects.</description><identifier>ISSN: 1938-5862</identifier><identifier>EISSN: 1938-6737</identifier><identifier>DOI: 10.1149/05806.0127ecst</identifier><language>eng</language><publisher>The Electrochemical Society, Inc</publisher><ispartof>ECS transactions, 2013-08, Vol.58 (6), p.127-132</ispartof><rights>2013 ECS - The Electrochemical Society</rights><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://iopscience.iop.org/article/10.1149/05806.0127ecst/pdf$$EPDF$$P50$$Giop$$H</linktopdf><link.rule.ids>314,780,784,27924,27925,53846,53893</link.rule.ids></links><search><creatorcontrib>Lim, SeungTaek</creatorcontrib><creatorcontrib>Ahn, Dukmin</creatorcontrib><creatorcontrib>Kim, Kihyun</creatorcontrib><creatorcontrib>Jung, Heechan</creatorcontrib><creatorcontrib>Lee, Byoungsu</creatorcontrib><creatorcontrib>Lee, Huihwan</creatorcontrib><creatorcontrib>Hwang, Hasub</creatorcontrib><title>Micro Unetched Oxide Defect during Buffered Oxide Etchant Process</title><title>ECS transactions</title><addtitle>ECS Trans</addtitle><description>There are two oxide regions, high and low voltage in NAND flash memory devices, in order to improve program speed and reliability. Generally, the two regions are achieved with pattern blocking by using PR(Photo Resistor) followed by etching of low voltage oxide with BOE(Buffered Oxide Etchant). However, as the 10nm scale NAND flash devices are massively manufactured, 0.2um size defects after oxide etching with BOE are newly detected. Partially unetched oxide defects in low voltage oxide region causes the thicker tunnel oxide and influences abnormal electron's tunneling. As the result, program and erase speed are declined on the relevant transistor, and it causes a yield drop by the electronic characteristics. As possible sources of the defects, the micro impurities in chemical or the micro bubbles from surfactant are suspected, but correct root cause is not yet known. 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Generally, the two regions are achieved with pattern blocking by using PR(Photo Resistor) followed by etching of low voltage oxide with BOE(Buffered Oxide Etchant). However, as the 10nm scale NAND flash devices are massively manufactured, 0.2um size defects after oxide etching with BOE are newly detected. Partially unetched oxide defects in low voltage oxide region causes the thicker tunnel oxide and influences abnormal electron's tunneling. As the result, program and erase speed are declined on the relevant transistor, and it causes a yield drop by the electronic characteristics. As possible sources of the defects, the micro impurities in chemical or the micro bubbles from surfactant are suspected, but correct root cause is not yet known. In this study, the effects of filter pore size and nozzle movement of cleaning equipment are examined in other to reduce the defects.</abstract><pub>The Electrochemical Society, Inc</pub><doi>10.1149/05806.0127ecst</doi><tpages>6</tpages></addata></record> |
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title | Micro Unetched Oxide Defect during Buffered Oxide Etchant Process |
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