(Invited) Important Challenges in Double Patterning Processes

Double Pattering process is one of the most promising lithography techniques for sub-40nm half-pitch technology node. Especially, Self-aligned spacer Double Patterning (SADP) has been adopted in HVM of NAND FLASH memory device[1], and it is expanding to employ in DRAM and logic device. If EUVL should not be ready on time, the industry will likely further extend DP to multiple patterning. Our proposed photo-resist core SADP has wide extendibility to Self-aligned Pitch-Tripling (SATP) and Pith-Quadrupling (SAQP) achieved 11nm hp as introduced in previous our study[2]. Sa-MP has been required to mitigate a process complexity and cost impact. Furthermore, Process variability, Pattern fidelity, CD metrology for sub 20nm pattern also has to be considered. Beside the invention of novel technical solutions, Double-patterning process is evolving steadily and its applicability is widened.