High Quality Silicon Cap Layer for 28nm and Beyond PMOS Processes
High quality embedded SiGe film with [Ge] concentration > 35% with Epitaxial grown Silicon (Si) cap layer has been demonstrated on a state-of-the-art 28nm logic flow. Si cap layer is a significant benefit to SiGe device for p-MOSFET contact resistance improvement but adversely affects the SiGe fi...
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creator | Liao, Chin I. Hsuan, Teng Chun Chien, Chin Cheng Chan, Michael Yang, Chan Lon Wu, J. Y. Ramachandran, Balasubramanian |
description | High quality embedded SiGe film with [Ge] concentration > 35% with Epitaxial grown Silicon (Si) cap layer has been demonstrated on a state-of-the-art 28nm logic flow. Si cap layer is a significant benefit to SiGe device for p-MOSFET contact resistance improvement but adversely affects the SiGe film strain relaxation especially for the high concentration [Ge] (> 35%). High quality, relaxation free SiGe film, with surface roughness improved from 4.21 to 0.65nm and 30% device contact resistance reduction are characterized in this work. |
doi_str_mv | 10.1149/05009.0419ecst |
format | Conference Proceeding |
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High quality, relaxation free SiGe film, with surface roughness improved from 4.21 to 0.65nm and 30% device contact resistance reduction are characterized in this work.</description><identifier>ISSN: 1938-5862</identifier><identifier>EISSN: 1938-6737</identifier><identifier>DOI: 10.1149/05009.0419ecst</identifier><language>eng</language><ispartof>ECS transactions, 2013, Vol.50 (9), p.419-424</ispartof><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><link.rule.ids>314,780,784,27924,27925</link.rule.ids></links><search><creatorcontrib>Liao, Chin I.</creatorcontrib><creatorcontrib>Hsuan, Teng Chun</creatorcontrib><creatorcontrib>Chien, Chin Cheng</creatorcontrib><creatorcontrib>Chan, Michael</creatorcontrib><creatorcontrib>Yang, Chan Lon</creatorcontrib><creatorcontrib>Wu, J. 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Si cap layer is a significant benefit to SiGe device for p-MOSFET contact resistance improvement but adversely affects the SiGe film strain relaxation especially for the high concentration [Ge] (> 35%). High quality, relaxation free SiGe film, with surface roughness improved from 4.21 to 0.65nm and 30% device contact resistance reduction are characterized in this work.</abstract><doi>10.1149/05009.0419ecst</doi><tpages>6</tpages><oa>free_for_read</oa></addata></record> |
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source | IOP Publishing Journals; Institute of Physics (IOP) Journals - HEAL-Link |
title | High Quality Silicon Cap Layer for 28nm and Beyond PMOS Processes |
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