POETS: An Event-driven Approach to Dissipative Particle Dynamics: Implementing a massively compute-intensive problem on a novel hard/software architecture

HPC clusters have become ever more expensive, both in terms of capital cost and energy consumption - some estimates suggest that competitive installations at the end of the next decade will require their own power station. One way around this looming problem is to design bespoke computing engines, b...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Veröffentlicht in:ACM transactions on parallel computing 2023-06, Vol.10 (2), p.1-32
Hauptverfasser: Brown, Andrew D., Beaumont, Jonathan R., Thomas, David B., Shillcock, Julian C., Naylor, Matthew F., Bragg, Graeme M., Vousden, Mark L., Moore, Simon W., Fleming, Shane T.
Format: Artikel
Sprache:eng
Schlagworte:
Online-Zugang:Volltext
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:HPC clusters have become ever more expensive, both in terms of capital cost and energy consumption - some estimates suggest that competitive installations at the end of the next decade will require their own power station. One way around this looming problem is to design bespoke computing engines, but while the performance benefits are good, the design costs are huge and cannot easily be amortized. POETS (Partially Ordered Event Triggered System) - the focus of this paper - seeks to exploit a middle way: the architecture is tuned to a specific algorithmic pattern, but within that constraint, is fully programmable. POETS software is quasi-imperative: the user defines a set of sequential event handlers, defines the topology of a (typically large) concurrent ensemble of these, and lets them interact. The 'solution' may be exfiltrated from the emergent behaviour of the ensemble. In this paper, we describe (briefly) the architecture, and an example computational chemistry application, dissipative particle dynamics (DPD). The DPD algorithm is traditionally implemented using parallel computational techniques, but we re-cast it as a concurrent compute problem which is then ideally suited to POETS. Our prototype system is realised on a cluster of 48 FPGAs providing 50K concurrent hardware threads, and we report performance speedups of over two orders of magnitude better than a single thread baseline comparator, and scaling behaviour that is almost constant. The results are validated against a "conventional" implementation.
ISSN:2329-4949
2329-4957
DOI:10.1145/3580372