SmartDR: Algorithms and Techniques for Fast Detailed Routing with Good Design Rule Handling

Detailed routing is one of the most time-consuming steps of physical synthesis of integrated circuits. Also, it is very challenging due to the complexity of the design rules that the router must obey. In this article, we present SmartDR, a detailed routing system that focuses on good design rule handling and fast runtime. To attend these objectives, we propose a novel pin access approach and a fast design rule aware A*-interval-based path search algorithm. The pin access method uses resource sharing ghost pin access paths with dynamic legalization check. We also propose a design rule check algorithm to detect thick metal shapes that are widely created using the proposed pin access method. The path search algorithm integrates design rule check on its core, handling many design rules that would not be possible to be solved by postprocessing. It is aware of the minimum area rule, the cut spacing of via cuts within the same path, and the via library. We also present a new technique to improve A*-based path search in detailed routing. The technique makes the path search algorithm aware of the global routing guides, accelerating the search. Using ISPD 2018 Contest benchmarks, our experiments show that our router is superior to the state-of-the-art routers that were also tested using the same benchmarks. Our router has presented, on average, 77.6% less runtime, 73.5% less design rule violations, with respect to Dr. CU 2.0, which is the better of the compared routers.