Fabrication and Characterization of NOR-Type Tri-Gate Flash Memory with Improved Inter-Poly Dielectric Layer by Rapid Thermal Oxidation

Floating-gate (FG)-type tri-gate flash memories with an improved inter-poly dielectric (IPD) layer have been successfully fabricated by introducing a newly developed rapid thermal oxidation (RTO) process, and their NOR-mode operation including threshold voltage ($V_{\text{t}}$) variations before and after one program/erase (P/E) cycle have been systematically investigated. It was experimentally confirmed that the gate breakdown voltage (BV \text{g ) is greatly increased from 12 to 19 V by introducing the RTO process thanks to the high quality and thin thermal silicon dioxide (SiO 2 ) formation on the FG surface and etched edge regions, which effectively blocks the leakage pass of the IPD layer. A source--drain (SD) breakdown voltage (BV \text{DS ) as high as 4.5 V was obtained even when the gate length ($L_{\text{g}}$) was as small as 117 nm. It was also experimentally confirmed that the memory window increases with increasing gate voltage ($V_{\text{g}}$) in NOR-mode programming thanks to the increased efficiency of channel hot electron (CHE) injection. The developed tri-gate flash memory with improved IPD layer is useful for the further scaling of NOR-type flash memory.