High Hole Mobility in 65 nm Strained Ge p-Channel Field Effect Transistors with HfO 2 Gate Dielectric

Biaxially-strained Ge p-channel field effect transistors (pFETs) have been fabricated for the first time in a 65 nm technology. The devices are designed to have a reduced effective oxide thickness (EOT) while maintaining minimized short channel effects. Low and high field transport has been studied...

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Veröffentlicht in:Japanese Journal of Applied Physics 2011-04, Vol.50 (4S), p.4
Hauptverfasser: Mitard, Jerome, Jaeger, Brice De, Eneman, Geert, Dobbie, Andrew, Myronov, Maksym, Kobayashi, Masaharu, Geypen, Jef, Bender, Hugo, Vincent, Benjamin, Krom, Raymond, Franco, Jacopo, Winderickx, Gillis, Vrancken, Evi, Vanherle, Wendy, Wang, Wei-E., Tseng, Joshua, Loo, Roger, Meyer, Kristin De, Caymax, Matty, Pantisano, Luigi, Leadley, David R., Meuris, Marc, Absil, Philippe P., Biesemans, Serge, Hoffmann, Thomas
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container_issue 4S
container_start_page 4
container_title Japanese Journal of Applied Physics
container_volume 50
creator Mitard, Jerome
Jaeger, Brice De
Eneman, Geert
Dobbie, Andrew
Myronov, Maksym
Kobayashi, Masaharu
Geypen, Jef
Bender, Hugo
Vincent, Benjamin
Krom, Raymond
Franco, Jacopo
Winderickx, Gillis
Vrancken, Evi
Vanherle, Wendy
Wang, Wei-E.
Tseng, Joshua
Loo, Roger
Meyer, Kristin De
Caymax, Matty
Pantisano, Luigi
Leadley, David R.
Meuris, Marc
Absil, Philippe P.
Biesemans, Serge
Hoffmann, Thomas
description Biaxially-strained Ge p-channel field effect transistors (pFETs) have been fabricated for the first time in a 65 nm technology. The devices are designed to have a reduced effective oxide thickness (EOT) while maintaining minimized short channel effects. Low and high field transport has been studied by in-depth electrical characterization, showing a high hole-mobility that is enhanced by up to 70% in the strained devices. The important role of pocket implants in degrading the drive current is highlighted. Using a judicious implantation scheme, we demonstrate a significant gain in on-current (up to 35%) for nanoscaled strained Ge pFETs. Simultaneous optimization of the gate metal and dielectric, together with the corresponding uniaxial stress engineering, is identified as a promising path for further performance enhancement.
doi_str_mv 10.1143/JJAP.50.04DC17
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