Computer Design of Source/Drain Extension Region Profile and Spacer Length in Tri-Gate Body-Tied Fin Field-Effect Transistors with High-$k$ Gate Dielectrics

The influences of source/drain extension region engineering and high-$k$ gate dielectrics on the device performance of tri-gate body-tied fin field-effect transistors (FinFETs) was investigated to achieve the International Technology Roadmap for Semiconductor (ITRS) projections for high-performance (HP) logic technology. The impact of lateral source/drain doping gradient ($L_{\text{dg}}$) and spacer length ($L_{\text{sp}}$) on short-channel effects (SCEs) was extensively analyzed by three-dimensional device simulation. Results show that a lateral doping gradient along with an appropriate spacer length not only can effectively control SCEs, resulting in a low off-current, but also can be optimized to achieve low values of intrinsic gate delay and high values of on-current. The ratio of spacer length to lateral doping gradient ($L_{\text{sp}}/L_{\text{dg}}$) between 2.7 and 4 is optimal for achieving a low intrinsic gate delay, a low off-current, and a high on/off-current ratio. The present work provides valuable design guidelines in the performance of tri-gate body-tied FinFETs with optimal source/drain extension region engineering and serves as a tool for optimizing important device and technological parameters.