Full-Chip Layout Optimization for Process Margin Enhancement Using Model-Based Hotspot Fixing System

As the design rule of integrated circuits is shrinking rapidly, it is necessary to use low-$k_{1}$ lithography technologies. With low-$k_{1}$ lithography, even if aggressive optical proximity correction is adopted, many sites become marginless spots, known as "hotspots". For this problem, hotspot fixer (HSF) in design-for-manufacturability flow has been studied. In our previous work, we indicated the feasibility of layout modification using a simple line/space sizing rule for metal layers in 65-nm-node logic devices. However, in view of the continuous design-rule shrinkage and design complication, a more flexible modification method has become necessary to fix various types of hotspots. In this work, we have developed a brute-force model-based HSF. To further reduce the processing time, the hybrid flow of rule- and model-based HSFs is studied. The feasibility of such hybrid flow is studied by applying it to the full-chip layout modification of a logic test chip.