Trench Sidewall Elimination Effect on Line-to-Line Leakage Current in Scalable Porous Silica ($k= 2.1$)/Cu Interconnect Structure

The sidewall film in low-$k$/copper interconnects is generally applied to protect the etched low-$k$ surface. However, the existence of this film will become a critical issue with shrinking device sizes. In this work, using intermetal low-$k$ film consisting of scalable porous silica ($k = 2.1$), we tried to eliminate the sidewall film by reducing pore size in 140-nm-pitched scalable porous silica/copper interconnects. Sufficient wiring resistance yield and low wiring capacitance were obtained even in the structure without sidewall. The degradation in the line-to-line leakage caused by the upper layer fabrication process was improved by this sidewall elimination. The mechanism of the leakage degradation was explained by the moisture diffusion from the upper layer, which reacted with the damage site generated by the sidewall formation process.