Dual-Gate Single-Electron Transistor with Silicon Nano Wire Channel and Surrounding Side Gates

In this paper, we propose a novel self-aligned dual-gate single-electron transistor having nano wire channel and surrounding side gates. By restricting the control gate effect to the top surface of the channel and intensifying the depletion effect through the surrounding side gates, the parasitic metal--oxide--silicon field-effect transistor (MOSFET) current and the quantum dot size are expected to be decreased. These advantages of the proposed structure are investigated through three-dimensional (3D) device simulation. In addition, the devices are fabricated by utilizing the silicon process and their electrical characteristics are analyzed at both room temperature and low temperature. Also, diverse device parameters are extracted from the measurement results, and they are systematically compared.