A Current-Mode Multiple-Resolution Edge-Filtering Complementary Metal Oxide Semiconductor Image Sensor Employing Self-Similitude Processing in Non-Subtraction Configuration

A non-subtraction configuration of the self-similitude image processing architecture has been developed for pixel-parallel multiple-resolution directional edge filtering. In contrast to the subtraction-separated configuration employed in our previous work, the subtraction operation has been entirely eliminated from the computation repertory of processing elements in the present configuration. As a result, the hardware organization of the multiple-resolution edge-filtering complementary metal oxide semiconductor (CMOS) image sensor has been greatly simplified, and a fully pixel-parallel self-similitude processing has been established without any complexity in interconnects. In addition, it has provided an opportunity to further apply the self-similitude architecture to other filtering operation like Gaussian filtering and Laplacian filtering. An analog edge-filtering chip implemented using current-mode computation capable of performing four-directional edge filtering at full, half, and quarter resolutions was designed and fabricated in a 0.18-\mbox{$\mu$m} five-metal CMOS technology. The concept has been verified by chip measurements, which show that the four-directional edge filtering at multiple resolutions is accomplished at 910 frames/s for $56{\times}56$-input images.