Depletion-Type Cell-Transistor on Partial Silicon-on-Insulator Substrate for 2× nm Generation Floating-Gate NAND Electrically Erasable Programmable Read Only Memory

To reduce the short-channel effect for memory cell transistors beyond 2× nm cell size for NAND electrically erasable programmable read only memories (EEPROMs), we propose a depletion-type cell transistor fabricated on a self-manufactured partial silicon-on-insulator (SOI) substrate by conventional LSI process and solid-phase epitaxy. The memory cell transistors with stack-gate show good program/erase properties and have the good S -factor of 309 mV/decade, wide enough threshold voltage ( V th ) window of 15 V between program and erase state, and fast enough program and erase time of 100 µs and 100 µs. And we observed no significant V th -window narrowing and increase in V th of about 1 V after 1000 cycling test. Operation bias sets of the depletion-type NAND EEPROM are as same as the sets of conventional NAND EEPROM and no peripheral circuit design change is needed. The short-channel effect is reduced substantially to available level for 2× nm size NAND EEPROM.