An Additional 12% Power Reduction in Practical Digital Chips with a Low-Power Design Using Post-Fabrication Clock-Timing Adjustment

An Additional 12% Power Reduction in Practical Digital Chips with a Low-Power Design Using Post-Fabrication Clock-Timing Adjustment

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Veröffentlicht in:Japanese Journal of Applied Physics 2009-04, Vol.48 (4S), p.4
Hauptverfasser: Susa, Tatsuya, Murakawa, Masahiro, Takahashi, Eiichi, Furuya, Tatsumi, Higuchi, Tetsuya, Furuichi, Shinji, Ueda, Yoshitaka, Wada, Atsushi
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container_issue 4S
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container_title Japanese Journal of Applied Physics
container_volume 48
creator Susa, Tatsuya
Murakawa, Masahiro
Takahashi, Eiichi
Furuya, Tatsumi
Higuchi, Tetsuya
Furuichi, Shinji
Ueda, Yoshitaka
Wada, Atsushi
description
doi_str_mv 10.1143/JJAP.48.04C076
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source IOP Publishing Journals; Institute of Physics (IOP) Journals - HEAL-Link
title An Additional 12% Power Reduction in Practical Digital Chips with a Low-Power Design Using Post-Fabrication Clock-Timing Adjustment
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