Optimum TiSi 2 Ohmic Contact Process for Sub-100 nm Devices

A defect which occurs at the corner of the metal/n+ contact bottom in direct contact (DC) of dynamic random access memories (DRAMs) with 100 nm technology and below is reported for the first time. The defect consists of Si stacking faults with a Si [011] zone axis and contains diffused titanium. The DC defect was responsible for high n+/p leakage current which increased with decreasing contact size. The defect can be completely removed by applying 700–900°C rapid thermal process (RTP) immediately after chemical vapor deposition (CVD)-Ti/TiN deposition, which transforms the deposited titanium to C54 titanium silicide. It is suggested that the generation of the DC defects is related to the incomplete phase transformation of titanium silicide.