Fabrication of Nanometer-Scale Vertical Metal-Insulator-Metal Tunnel Junctions Using a Silicon-on-Insulator Substrate

We have developed a vertical metal-insulator-metal (MIM) junctions fabrication process using a silicon on insulator (SOI) substrate. The diameter of the contact-hole of the top SiO 2 layer tends to saturate with an increase in exposed dose, and a mask with a contact-hole of a minimum diameter of about 15 nm was successfully fabricated. An aluminum vertical array of two MIM junctions exhibited the typical current-voltage ( I-V ) characteristics of tunnel junctions at room temperature. However, they showed a large dispersion of conductance and a large leakage current after repeated I-V measurements of 30–50 times, probably because of the granular structure of the deposited Al films. A chromium vertical array of two MIM junctions exhibited the linear I-V characteristics of a metal wire at room temperature just after fabrication. They exhibited the typical I-V characteristics of tunnel junctions after 300°C annealing, probably because of the structural transition of chromium oxide films from the low-resistance CrO 2 to the high-resistance Cr 2 O 3 .