Simple Model for Gate-Voltage Dependent Parasitic Resistancein Short Channel Lightly Doped Drain Metal Oxide Semiconductor Field Effect Transistors

The parasitic resistance of the lightly doped drain (LDD) is modeled as parallel combination of the resistance of an accumulation layer formed at the surface of the LDD, and that of the bulk LDD. In saturation regime, velocity saturation in both the channel and the LDD is taken into account and the resulting resistance shows a quasi-linear behavior with respect to the gate voltage.