Josephson NOR decoder circuit for Josephson memory arrays

A new type of Josephson decoder circuit has been devised and designed. The fundamental operation principles for the circuit are based on modification of the address signal multiplicand A 0 ·A 1 ·...·A n to NOR form. Implementation of this principle gives large operation margins and high operation speed. In building the decoder, a new large fan-out gate, inverter circuit and timed bias circuit were devised. Proper operation of the decoder was confirmed by computer simulations, and the operation times for the 5-to-32 decoder obtained were about 300 ps for nominal conditions and 50 ps for the best conditions. The designed operation bias margin for the decoder is ±37%.