Reduction of Output Conductance in Vertical InGaAs Channel Metal--Insulator--Semiconductor Field-Effect Transistor Using Heavily Doped Drain Region

In this paper, the reduction in the output conductance ($g_{\text{o}}$) of a vertical InGaAs channel metal--insulator--semiconductor field-effect transistor (MISFET) is reported. While vertical InGaAs channel MISFETs exhibit a high drain current density, their large $g_{\text{o}}$ is a disadvantage. Monte Carlo simulation suggests that the large $g_{\text{o}}$ might be caused by conduction band bending due to many space charges between the gate and drain. To prevent conduction band bending, a device in which the gate electrode overlaps with the drain region was proposed and fabricated. Consequently, $g_{\text{o}}$ was decreased from 3.2 to 1 S/mm.