Low-voltage arithmetic units based on fully depleted SOI CMOS nanotransistors

Approaches to the development of low-voltage low-power-demand arithmetic units on the basis of silicon-on-insulator nanotransistors are considered. The characteristics of physical models of one- and eight-bit adders based on fully depleted silicon-on-insulator complementary metal-oxide-semiconductor...

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Veröffentlicht in:Russian microelectronics 2010, Vol.39 (1), p.54-62
1. Verfasser: Masal’skii, N. V.
Format: Artikel
Sprache:eng
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Zusammenfassung:Approaches to the development of low-voltage low-power-demand arithmetic units on the basis of silicon-on-insulator nanotransistors are considered. The characteristics of physical models of one- and eight-bit adders based on fully depleted silicon-on-insulator complementary metal-oxide-semiconductor nanotransistors with different topological parameters are numerically analyzed. For some selected elements, the dependences of the delay time and switching power on supply voltage below 1 V are studied for different voltages at the back gate of the transistor.
ISSN:1063-7397
1608-3415
DOI:10.1134/S1063739710010075