Effects of trapped charges on Hg-Schottky capacitance–voltage measurements of n-type epitaxial silicon wafers

The effects of surface charge in the oxide layer for Hg-Schottky capacitance–voltage (C–V) measurements have been discussed in detail. The accumulation of majority carriers at the Si surface has been identified as a major factor controlling the stability and accuracy of the Hg-Schottky C–V measurement. For n-type wafers, the fixed oxide charge in Si oxide layer induces electron accumulation at the oxide/Si interface. This electron accumulation cannot be dissipated until a depleting voltage as high as −5.0 V is applied depending on the preparation of the oxide layer. It has been found that introducing Cu during the growth of the oxide layer can produce a deep trap level in the oxide. Pre-electrical-field stress at 5 MV/cm for 5 s can fill these traps and eliminate electron accumulation, resulting in a stable and accurate C–V measurement. Our results on p-type wafers show that the fixed oxide charge in the oxide layer can establish a surface depletion condition and produce a stable and accurate C–V measurement. With these experimental results, we propose that Si oxide layer can improve the stability and accuracy of the Hg-Schottky C–V measurement for both n- and p-type wafers. For n-type wafers, pre-electrical stress and a Si oxide layer with deep electron trap level are necessary; for p-type wafers, only the fixed oxide charge is needed.