Fabrication of 22nm half-pitch silicon lines by single-exposure self-aligned spatial-frequency doubling
The relentless progression of semiconductor technology to smaller feature sizes will likely soon outstrip the theoretical linear system limits of today’s optical lithography tools (a half-pitch of λ∕4n or 34nm with a 193nm wavelength source and water immersion). We demonstrate a self-aligned process...
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Veröffentlicht in: | Journal of vacuum science & technology. B, Microelectronics and nanometer structures processing, measurement and phenomena Microelectronics and nanometer structures processing, measurement and phenomena, 2007-11, Vol.25 (6), p.2224-2227 |
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Format: | Artikel |
Sprache: | eng |
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Zusammenfassung: | The relentless progression of semiconductor technology to smaller feature sizes will likely soon outstrip the theoretical linear system limits of today’s optical lithography tools (a half-pitch of λ∕4n or 34nm with a 193nm wavelength source and water immersion). We demonstrate a self-aligned process involving only a single lithographic exposure followed by spatial-frequency doubling that results a half-scaling of the original pattern and have achieved a 22nm half-pitch pattern with 193nm water immersion. A lithographic pitch of 89nm was realized with a 193nm ArF-excimer laser source and de-ionized-water immersion interferometric lithography. A self-aligned spatial-frequency doubling technique, taking advantage of the well-known anisotropic etching of silicon by KOH, was used to affect the frequency doubling. A protective layer (metal) was deposited parallel to the (110) direction of a (100) silicon wafer and the sample was immersed in an appropriate KOH solution, resulting in a series of 44.5nm opening width V-grooves terminated in 57° (111) faces etched into the silicon through the mask openings. The metal mask was removed to expose the previously protected high-etch rate (100) surface of the sample for a second wet KOH etch. This results in a pattern at twice the original spatial frequency. A frequency-doubled pitch of 44.5nm was achieved. An alternate, manufacturing friendly, processing scheme related to standard gate sidewall passivation is proposed. |
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ISSN: | 1071-1023 1520-8567 |
DOI: | 10.1116/1.2801889 |