Bias-temperature stress analysis of Cu∕ultrathin Ta∕SiO2∕Si interconnect structure

Bias-temperature stress test was used to evaluate the efficiency of an ultrathin Ta diffusion barrier in Cu interconnects by assessing the failure mode of the Cu interconnect structure. Samples are stressed up to failure in order to study the actual failure mode of fabricated MOS capacitors. The time-to-failure (TTF) of samples is estimated to be at least 14 years under standard operating conditions, which is determined by extrapolating TTFs of current–time (I–t) curves measured at accelerated test conditions. The calculated activation energies of the capacitors is within range of normal time-dependent dielectric breakdown (TDDB) activation energies, suggesting TDDB-related failure. Tof-SIMS and I–t analyses strongly suggest a mixed mode failure mechanism in the capacitors, where Cu+ ion contamination is dominant at low field and high temperature stress conditions, while TDDB dominates at other conditions.