A 0.9-5.8-GHz Software-Defined Receiver RF Front-End With Transformer-Based Current-Gain Boosting and Harmonic Rejection Calibration
A 0.9-5.8-GHz receiver RF front-end (RFE) integrating a dual-band low-noise transconductance amplifier (LNTA), a passive harmonic-rejection (HR) down-conversion mixer, and an all-digital frequency synthesizer for software-defined radios are presented. A switchable three-coil transformer acting as th...
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| Veröffentlicht in: | IEEE transactions on very large scale integration (VLSI) systems 2017-08, Vol.25 (8), p.2371-2382 |
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| container_title | IEEE transactions on very large scale integration (VLSI) systems |
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| creator | Liang Wu Ng, Alan W. L. Shiyuan Zheng Hiu Fai Leung Yue Chao Alvin Li Luong, Howard C. |
| description | A 0.9-5.8-GHz receiver RF front-end (RFE) integrating a dual-band low-noise transconductance amplifier (LNTA), a passive harmonic-rejection (HR) down-conversion mixer, and an all-digital frequency synthesizer for software-defined radios are presented. A switchable three-coil transformer acting as the interface between the LNTA and the mixer features current-gain boosting in addition to wideband operation. Automatic local oscillator phase-error detection and calibration circuitry is implemented for the mixers to achieve high HR ratio (HRR). Fabricated in 65-nm CMOS, the RFE measures the noise figure between 2.9 and 3.8 dB, the third-order input intercept point (IIP3) between -1.6 and -12.8 dBm, the third-order HRR of 81 dB, and the fifth-order HRR of 70 dB, while consuming 66-82 mA from a 1.2-V supply and occupying a chip area of 4.2 mm 2 . |
| doi_str_mv | 10.1109/TVLSI.2017.2695719 |
| format | Article |
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L. ; Shiyuan Zheng ; Hiu Fai Leung ; Yue Chao ; Alvin Li ; Luong, Howard C.</creator><creatorcontrib>Liang Wu ; Ng, Alan W. L. ; Shiyuan Zheng ; Hiu Fai Leung ; Yue Chao ; Alvin Li ; Luong, Howard C.</creatorcontrib><description>A 0.9-5.8-GHz receiver RF front-end (RFE) integrating a dual-band low-noise transconductance amplifier (LNTA), a passive harmonic-rejection (HR) down-conversion mixer, and an all-digital frequency synthesizer for software-defined radios are presented. A switchable three-coil transformer acting as the interface between the LNTA and the mixer features current-gain boosting in addition to wideband operation. Automatic local oscillator phase-error detection and calibration circuitry is implemented for the mixers to achieve high HR ratio (HRR). Fabricated in 65-nm CMOS, the RFE measures the noise figure between 2.9 and 3.8 dB, the third-order input intercept point (IIP3) between -1.6 and -12.8 dBm, the third-order HRR of 81 dB, and the fifth-order HRR of 70 dB, while consuming 66-82 mA from a 1.2-V supply and occupying a chip area of 4.2 mm 2 .</description><identifier>ISSN: 1063-8210</identifier><identifier>EISSN: 1557-9999</identifier><identifier>DOI: 10.1109/TVLSI.2017.2695719</identifier><identifier>CODEN: IEVSE9</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>All-digital phase-locked loop (ADPLL) ; Amplification ; Boosting ; Broadband ; Calibration ; Circuits ; CMOS ; Coils ; Error detection ; frequency synthesizer (FS) ; Gain ; gain boosting ; harmonic rejection (HR) ; low-noise transconductance amplifier (LNTA) ; Mixers ; multiband ; Noise levels ; Noise measurement ; passive mixer ; Radio frequency ; Receivers ; Rejection ; RF front-end (RFE) ; software-defined radio (SDR) ; Transconductance ; transformer ; Transformers ; Wireless communication</subject><ispartof>IEEE transactions on very large scale integration (VLSI) systems, 2017-08, Vol.25 (8), p.2371-2382</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2017</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c295t-1cc117683b23a3f257de5141f9abc0fe198d8848cd163522418b3b2c36f36b473</citedby><cites>FETCH-LOGICAL-c295t-1cc117683b23a3f257de5141f9abc0fe198d8848cd163522418b3b2c36f36b473</cites><orcidid>0000-0003-2944-3035</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/7918625$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,777,781,793,27905,27906,54739</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/7918625$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Liang Wu</creatorcontrib><creatorcontrib>Ng, Alan W. L.</creatorcontrib><creatorcontrib>Shiyuan Zheng</creatorcontrib><creatorcontrib>Hiu Fai Leung</creatorcontrib><creatorcontrib>Yue Chao</creatorcontrib><creatorcontrib>Alvin Li</creatorcontrib><creatorcontrib>Luong, Howard C.</creatorcontrib><title>A 0.9-5.8-GHz Software-Defined Receiver RF Front-End With Transformer-Based Current-Gain Boosting and Harmonic Rejection Calibration</title><title>IEEE transactions on very large scale integration (VLSI) systems</title><addtitle>TVLSI</addtitle><description>A 0.9-5.8-GHz receiver RF front-end (RFE) integrating a dual-band low-noise transconductance amplifier (LNTA), a passive harmonic-rejection (HR) down-conversion mixer, and an all-digital frequency synthesizer for software-defined radios are presented. A switchable three-coil transformer acting as the interface between the LNTA and the mixer features current-gain boosting in addition to wideband operation. Automatic local oscillator phase-error detection and calibration circuitry is implemented for the mixers to achieve high HR ratio (HRR). Fabricated in 65-nm CMOS, the RFE measures the noise figure between 2.9 and 3.8 dB, the third-order input intercept point (IIP3) between -1.6 and -12.8 dBm, the third-order HRR of 81 dB, and the fifth-order HRR of 70 dB, while consuming 66-82 mA from a 1.2-V supply and occupying a chip area of 4.2 mm 2 .</description><subject>All-digital phase-locked loop (ADPLL)</subject><subject>Amplification</subject><subject>Boosting</subject><subject>Broadband</subject><subject>Calibration</subject><subject>Circuits</subject><subject>CMOS</subject><subject>Coils</subject><subject>Error detection</subject><subject>frequency synthesizer (FS)</subject><subject>Gain</subject><subject>gain boosting</subject><subject>harmonic rejection (HR)</subject><subject>low-noise transconductance amplifier (LNTA)</subject><subject>Mixers</subject><subject>multiband</subject><subject>Noise levels</subject><subject>Noise measurement</subject><subject>passive mixer</subject><subject>Radio frequency</subject><subject>Receivers</subject><subject>Rejection</subject><subject>RF front-end (RFE)</subject><subject>software-defined radio (SDR)</subject><subject>Transconductance</subject><subject>transformer</subject><subject>Transformers</subject><subject>Wireless communication</subject><issn>1063-8210</issn><issn>1557-9999</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2017</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9kMFuEzEQhlcIJErhBeBiibO3Hnu9to9taJJKkZDaAMeV1zsGR41d7E0RnHlwnKZiLjOH7_9H-prmPbAWgJmL7dfN3U3LGaiW90YqMC-aM5BSUVPnZb1ZL6jmwF43b0rZMQZdZ9hZ8_eSsNZQ2Wq6Wv8hd8nPv2xG-gl9iDiRW3QYHjGT2yVZ5hRneh0n8i3MP8g221h8ynvM9MqWCi8OOWNFVjZEcpVSmUP8TmwNrG3epxhc7duhm0OKZGHvw5jt8X7bvPL2vuC7533efFlebxdruvm8ullcbqjjRs4UnANQvRYjF1Z4LtWEEjrwxo6OeQSjJ6077SboheS8Az1W1onei37slDhvPp56H3L6ecAyD7t0yLG-HMBwoRTrQFaKnyiXUykZ_fCQw97m3wOw4Wh7eLI9HG0Pz7Zr6MMpFBDxf0AZ0D2X4h_X7npM</recordid><startdate>20170801</startdate><enddate>20170801</enddate><creator>Liang Wu</creator><creator>Ng, Alan W. L.</creator><creator>Shiyuan Zheng</creator><creator>Hiu Fai Leung</creator><creator>Yue Chao</creator><creator>Alvin Li</creator><creator>Luong, Howard C.</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><orcidid>https://orcid.org/0000-0003-2944-3035</orcidid></search><sort><creationdate>20170801</creationdate><title>A 0.9-5.8-GHz Software-Defined Receiver RF Front-End With Transformer-Based Current-Gain Boosting and Harmonic Rejection Calibration</title><author>Liang Wu ; Ng, Alan W. L. ; Shiyuan Zheng ; Hiu Fai Leung ; Yue Chao ; Alvin Li ; Luong, Howard C.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c295t-1cc117683b23a3f257de5141f9abc0fe198d8848cd163522418b3b2c36f36b473</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2017</creationdate><topic>All-digital phase-locked loop (ADPLL)</topic><topic>Amplification</topic><topic>Boosting</topic><topic>Broadband</topic><topic>Calibration</topic><topic>Circuits</topic><topic>CMOS</topic><topic>Coils</topic><topic>Error detection</topic><topic>frequency synthesizer (FS)</topic><topic>Gain</topic><topic>gain boosting</topic><topic>harmonic rejection (HR)</topic><topic>low-noise transconductance amplifier (LNTA)</topic><topic>Mixers</topic><topic>multiband</topic><topic>Noise levels</topic><topic>Noise measurement</topic><topic>passive mixer</topic><topic>Radio frequency</topic><topic>Receivers</topic><topic>Rejection</topic><topic>RF front-end (RFE)</topic><topic>software-defined radio (SDR)</topic><topic>Transconductance</topic><topic>transformer</topic><topic>Transformers</topic><topic>Wireless communication</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Liang Wu</creatorcontrib><creatorcontrib>Ng, Alan W. L.</creatorcontrib><creatorcontrib>Shiyuan Zheng</creatorcontrib><creatorcontrib>Hiu Fai Leung</creatorcontrib><creatorcontrib>Yue Chao</creatorcontrib><creatorcontrib>Alvin Li</creatorcontrib><creatorcontrib>Luong, Howard C.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEEE transactions on very large scale integration (VLSI) systems</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Liang Wu</au><au>Ng, Alan W. L.</au><au>Shiyuan Zheng</au><au>Hiu Fai Leung</au><au>Yue Chao</au><au>Alvin Li</au><au>Luong, Howard C.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A 0.9-5.8-GHz Software-Defined Receiver RF Front-End With Transformer-Based Current-Gain Boosting and Harmonic Rejection Calibration</atitle><jtitle>IEEE transactions on very large scale integration (VLSI) systems</jtitle><stitle>TVLSI</stitle><date>2017-08-01</date><risdate>2017</risdate><volume>25</volume><issue>8</issue><spage>2371</spage><epage>2382</epage><pages>2371-2382</pages><issn>1063-8210</issn><eissn>1557-9999</eissn><coden>IEVSE9</coden><abstract>A 0.9-5.8-GHz receiver RF front-end (RFE) integrating a dual-band low-noise transconductance amplifier (LNTA), a passive harmonic-rejection (HR) down-conversion mixer, and an all-digital frequency synthesizer for software-defined radios are presented. A switchable three-coil transformer acting as the interface between the LNTA and the mixer features current-gain boosting in addition to wideband operation. Automatic local oscillator phase-error detection and calibration circuitry is implemented for the mixers to achieve high HR ratio (HRR). Fabricated in 65-nm CMOS, the RFE measures the noise figure between 2.9 and 3.8 dB, the third-order input intercept point (IIP3) between -1.6 and -12.8 dBm, the third-order HRR of 81 dB, and the fifth-order HRR of 70 dB, while consuming 66-82 mA from a 1.2-V supply and occupying a chip area of 4.2 mm 2 .</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/TVLSI.2017.2695719</doi><tpages>12</tpages><orcidid>https://orcid.org/0000-0003-2944-3035</orcidid></addata></record> |
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| subjects | All-digital phase-locked loop (ADPLL) Amplification Boosting Broadband Calibration Circuits CMOS Coils Error detection frequency synthesizer (FS) Gain gain boosting harmonic rejection (HR) low-noise transconductance amplifier (LNTA) Mixers multiband Noise levels Noise measurement passive mixer Radio frequency Receivers Rejection RF front-end (RFE) software-defined radio (SDR) Transconductance transformer Transformers Wireless communication |
| title | A 0.9-5.8-GHz Software-Defined Receiver RF Front-End With Transformer-Based Current-Gain Boosting and Harmonic Rejection Calibration |
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