A Fully On-Chip PT-Invariant Transconductor

This brief presents a novel process and temperature (PT)-invariant transconductor, fabricated and tested in 180-nm CMOS technology. It uses a novel bias circuit for implementing a PT-invariant transconductor using a MOSFET in triode region. Measurements show that the transconductance varies only by...

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Veröffentlicht in:IEEE transactions on very large scale integration (VLSI) systems 2015-09, Vol.23 (9), p.1961-1964
Hauptverfasser: Amaravati, Anvesha, Dave, Marshnil, Baghini, Maryam Shojaei, Sharma, Dinesh K.
Format: Artikel
Sprache:eng
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Zusammenfassung:This brief presents a novel process and temperature (PT)-invariant transconductor, fabricated and tested in 180-nm CMOS technology. It uses a novel bias circuit for implementing a PT-invariant transconductor using a MOSFET in triode region. Measurements show that the transconductance varies only by ±3.4% across 18 fabricated chips and over temperatures ranging from 25 °C to 100 °C. Simulations show that variation of the transconductance across process corners is ±6.7% and across temperature range of 0 °C to 100 °C is ±1.6%. The proposed PT-invariant transconductor has the minimum variation among the fully on-chip transconductors reported so far. The proposed circuit consumes 136 μW of power.
ISSN:1063-8210
1557-9999
DOI:10.1109/TVLSI.2014.2347346