Pipelined Radix- 2^ Feedforward FFT Architectures
The appearance of radix-2 2 was a milestone in the design of pipelined FFT hardware architectures. Later, radix-2 2 was extended to radix-2 k . However, radix-2 k was only proposed for single-path delay feedback (SDF) architectures, but not for feedforward ones, also called multi-path delay commutat...
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| Veröffentlicht in: | IEEE transactions on very large scale integration (VLSI) systems 2013-01, Vol.21 (1), p.23-32 |
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| container_title | IEEE transactions on very large scale integration (VLSI) systems |
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| creator | Garrido, M. Grajal, J. Sanchez, M. A. Gustafsson, O. |
| description | The appearance of radix-2 2 was a milestone in the design of pipelined FFT hardware architectures. Later, radix-2 2 was extended to radix-2 k . However, radix-2 k was only proposed for single-path delay feedback (SDF) architectures, but not for feedforward ones, also called multi-path delay commutator (MDC). This paper presents the radix-2 k feedforward (MDC) FFT architectures. In feedforward architectures radix-2 k can be used for any number of parallel samples which is a power of two. Furthermore, both decimation in frequency (DIF) and decimation in time (DIT) decompositions can be used. In addition to this, the designs can achieve very high throughputs, which makes them suitable for the most demanding applications. Indeed, the proposed radix-2 k feedforward architectures require fewer hardware resources than parallel feedback ones, also called multi-path delay feedback (MDF), when several samples in parallel must be processed. As a result, the proposed radix-2 k feedforward architectures not only offer an attractive solution for current applications, but also open up a new research line on feedforward structures. |
| doi_str_mv | 10.1109/TVLSI.2011.2178275 |
| format | Article |
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Indeed, the proposed radix-2 k feedforward architectures require fewer hardware resources than parallel feedback ones, also called multi-path delay feedback (MDF), when several samples in parallel must be processed. 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A.</creatorcontrib><creatorcontrib>Gustafsson, O.</creatorcontrib><title>Pipelined Radix- 2^ Feedforward FFT Architectures</title><title>IEEE transactions on very large scale integration (VLSI) systems</title><addtitle>TVLSI</addtitle><description>The appearance of radix-2 2 was a milestone in the design of pipelined FFT hardware architectures. Later, radix-2 2 was extended to radix-2 k . However, radix-2 k was only proposed for single-path delay feedback (SDF) architectures, but not for feedforward ones, also called multi-path delay commutator (MDC). This paper presents the radix-2 k feedforward (MDC) FFT architectures. In feedforward architectures radix-2 k can be used for any number of parallel samples which is a power of two. Furthermore, both decimation in frequency (DIF) and decimation in time (DIT) decompositions can be used. In addition to this, the designs can achieve very high throughputs, which makes them suitable for the most demanding applications. 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As a result, the proposed radix-2 k feedforward architectures not only offer an attractive solution for current applications, but also open up a new research line on feedforward structures.</description><subject>Clocks</subject><subject>Computer architecture</subject><subject>Delay</subject><subject>Fast Fourier transform (FFT)</subject><subject>Feedforward neural networks</subject><subject>Indexes</subject><subject>multipath delay commutator (MDC)</subject><subject>Multiplexing</subject><subject>pipelined architecture</subject><subject>radix- 2^{k}</subject><subject>TECHNOLOGY</subject><subject>TEKNIKVETENSKAP</subject><subject>Throughput</subject><subject>VLSI</subject><issn>1063-8210</issn><issn>1557-9999</issn><issn>1557-9999</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2013</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><sourceid>D8T</sourceid><recordid>eNo9kMFOAjEQQBujiYj-gF72A1zsTHe37ZGgqyQkGkWONqU71Rp0SQtB_95FCHOZObw3h8fYJfABANc309nkZTxADjBAkAplecR6UJYy190cdzevRK4Q-Ck7S-mTcygKzXsMnsKSFuGbmuzZNuEnz_Atq4ka38aNjU1W19NsGN1HWJFbrSOlc3bi7SLRxX732Wt9Nx095JPH-_FoOMmdKNQqF66xFr2VQvk5Oum81NSo0hFKjdphJSpRWK-8xtJLKiUp1FxrBKCOEX12vfubNrRcz80yhi8bf01rg7kNs6Fp47tZhLVRSlS8w3GHu9imFMkfBOBm28j8NzLbRmbfqJOudlIgooNQASgBlfgD1LJiKg</recordid><startdate>201301</startdate><enddate>201301</enddate><creator>Garrido, M.</creator><creator>Grajal, J.</creator><creator>Sanchez, M. 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A. ; Gustafsson, O.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c348t-3cdaa2fa738fb2c7cf79ed85ce27929c263634af8f925f7e57e829099211ee273</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2013</creationdate><topic>Clocks</topic><topic>Computer architecture</topic><topic>Delay</topic><topic>Fast Fourier transform (FFT)</topic><topic>Feedforward neural networks</topic><topic>Indexes</topic><topic>multipath delay commutator (MDC)</topic><topic>Multiplexing</topic><topic>pipelined architecture</topic><topic>radix- 2^{k}</topic><topic>TECHNOLOGY</topic><topic>TEKNIKVETENSKAP</topic><topic>Throughput</topic><topic>VLSI</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Garrido, M.</creatorcontrib><creatorcontrib>Grajal, J.</creatorcontrib><creatorcontrib>Sanchez, M. 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| source | IEEE Electronic Library (IEL) |
| subjects | Clocks Computer architecture Delay Fast Fourier transform (FFT) Feedforward neural networks Indexes multipath delay commutator (MDC) Multiplexing pipelined architecture radix- 2^{k} TECHNOLOGY TEKNIKVETENSKAP Throughput VLSI |
| title | Pipelined Radix- 2^ Feedforward FFT Architectures |
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