Analysis of Power-via-Induced Quasi-Quarter-Wavelength Resonance to Reduce Crosstalk
Currently, power pins are increasingly used in package design to serve a dual purpose: to support crosstalk isolation between high-speed signals and to provide power delivery to serializer/deserializer input/output. This approach can reduce the overall pin count and subsequently limit the package bo...
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| Veröffentlicht in: | IEEE transactions on signal and power integrity 2022, Vol.1, p.121-129 |
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| container_title | IEEE transactions on signal and power integrity |
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| creator | Bai, Siqi Liu, Yuanzhuo Lee, Jongjoo Chen, Bichen Venkataraman, Srinivas Wang, Xu Pu, Bo Fan, Jun Kim, DongHyun |
| description | Currently, power pins are increasingly used in package design to serve a dual purpose: to support crosstalk isolation between high-speed signals and to provide power delivery to serializer/deserializer input/output. This approach can reduce the overall pin count and subsequently limit the package body size to remain within a ball grid array form factor. However, for printed circuit boards (PCBs) in which power vias are adjacent to signal vias, increased far-end crosstalk (FEXT) and resonance in insertion loss can be observed, due to the quasi-quarter-wavelength resonance of the power via stub. Using an analytical model and 3-D full-wave simulation models, a physical explanation for this unexpected resonance in differential signal pairs is proposed. Considering the difficulty in changing the pin map of the IC package, several PCB layouts are proposed to eliminate the power-via-induced quasi-quarter-wavelength resonance without the need to change the package pin map. Upon application of the proposed methods, the resonance is eliminated, and the FEXT is reduced. |
| doi_str_mv | 10.1109/TSIPI.2022.3209138 |
| format | Article |
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Upon application of the proposed methods, the resonance is eliminated, and the FEXT is reduced.</description><subject>Analytical models</subject><subject>Crosstalk</subject><subject>Crosstalk mitigation</subject><subject>Insertion loss</subject><subject>Loss measurement</subject><subject>noise reduction</subject><subject>physics-based via model</subject><subject>pin map patterns</subject><subject>Resonant frequency</subject><subject>serializer/deserializer (Serdes)</subject><subject>Signal integrity</subject><subject>Transmission line measurements</subject><issn>2768-1866</issn><issn>2768-1866</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2022</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNpNkNtKw0AQhhdRsNS-gN7kBbbOHrKbvSzBQ6Bg1YCXYZPMajQmkk0rfXs3tog3c_z_GfgIuWSwZAzMdf6cbbIlB86XgoNhIjkhM65VQlmi1Om_-pwsvH8HAG5UkKkZyVedbfe-8VHvok3_jQPdNZZmXb2tsI4et9Y3NMRhDJsXu8MWu9fxLXpC33e2qzAa-9BM6igdeu9H235ckDNnW4-LY56T_PYmT-_p-uEuS1drWikhaWlibkFDJRRztRJOGyYxBqaNq8u4FkbFso41c0mYSbTGSqkY59qBKQHFnPDD2Wp6PKArvobm0w77gkExkSl-yRQTmeJIJpiuDqYGEf8MxoBMlBQ_pRdfLg</recordid><startdate>2022</startdate><enddate>2022</enddate><creator>Bai, Siqi</creator><creator>Liu, Yuanzhuo</creator><creator>Lee, Jongjoo</creator><creator>Chen, Bichen</creator><creator>Venkataraman, Srinivas</creator><creator>Wang, Xu</creator><creator>Pu, Bo</creator><creator>Fan, Jun</creator><creator>Kim, DongHyun</creator><general>IEEE</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><orcidid>https://orcid.org/0000-0003-2738-9549</orcidid><orcidid>https://orcid.org/0000-0002-6232-7637</orcidid><orcidid>https://orcid.org/0000-0003-0595-8085</orcidid></search><sort><creationdate>2022</creationdate><title>Analysis of Power-via-Induced Quasi-Quarter-Wavelength Resonance to Reduce Crosstalk</title><author>Bai, Siqi ; Liu, Yuanzhuo ; Lee, Jongjoo ; Chen, Bichen ; Venkataraman, Srinivas ; Wang, Xu ; Pu, Bo ; Fan, Jun ; Kim, DongHyun</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c634-b952a070c361fd63f7914e50179fdb5d39654d571f80174ea9a4461227f09b0e3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2022</creationdate><topic>Analytical models</topic><topic>Crosstalk</topic><topic>Crosstalk mitigation</topic><topic>Insertion loss</topic><topic>Loss measurement</topic><topic>noise reduction</topic><topic>physics-based via model</topic><topic>pin map patterns</topic><topic>Resonant frequency</topic><topic>serializer/deserializer (Serdes)</topic><topic>Signal integrity</topic><topic>Transmission line measurements</topic><toplevel>online_resources</toplevel><creatorcontrib>Bai, Siqi</creatorcontrib><creatorcontrib>Liu, Yuanzhuo</creatorcontrib><creatorcontrib>Lee, Jongjoo</creatorcontrib><creatorcontrib>Chen, Bichen</creatorcontrib><creatorcontrib>Venkataraman, Srinivas</creatorcontrib><creatorcontrib>Wang, Xu</creatorcontrib><creatorcontrib>Pu, Bo</creatorcontrib><creatorcontrib>Fan, Jun</creatorcontrib><creatorcontrib>Kim, DongHyun</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><jtitle>IEEE transactions on signal and power integrity</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Bai, Siqi</au><au>Liu, Yuanzhuo</au><au>Lee, Jongjoo</au><au>Chen, Bichen</au><au>Venkataraman, Srinivas</au><au>Wang, Xu</au><au>Pu, Bo</au><au>Fan, Jun</au><au>Kim, DongHyun</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Analysis of Power-via-Induced Quasi-Quarter-Wavelength Resonance to Reduce Crosstalk</atitle><jtitle>IEEE transactions on signal and power integrity</jtitle><stitle>TSIPI</stitle><date>2022</date><risdate>2022</risdate><volume>1</volume><spage>121</spage><epage>129</epage><pages>121-129</pages><issn>2768-1866</issn><eissn>2768-1866</eissn><coden>ITSPBJ</coden><abstract>Currently, power pins are increasingly used in package design to serve a dual purpose: to support crosstalk isolation between high-speed signals and to provide power delivery to serializer/deserializer input/output. This approach can reduce the overall pin count and subsequently limit the package body size to remain within a ball grid array form factor. However, for printed circuit boards (PCBs) in which power vias are adjacent to signal vias, increased far-end crosstalk (FEXT) and resonance in insertion loss can be observed, due to the quasi-quarter-wavelength resonance of the power via stub. Using an analytical model and 3-D full-wave simulation models, a physical explanation for this unexpected resonance in differential signal pairs is proposed. Considering the difficulty in changing the pin map of the IC package, several PCB layouts are proposed to eliminate the power-via-induced quasi-quarter-wavelength resonance without the need to change the package pin map. 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| subjects | Analytical models Crosstalk Crosstalk mitigation Insertion loss Loss measurement noise reduction physics-based via model pin map patterns Resonant frequency serializer/deserializer (Serdes) Signal integrity Transmission line measurements |
| title | Analysis of Power-via-Induced Quasi-Quarter-Wavelength Resonance to Reduce Crosstalk |
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