A Family of Dual-Boost Bridgeless Five-Level Rectifiers With Common-Core Inductors

In this article, a family of dual-boost bridgeless five-level rectifiers with common-core inductors is proposed, which is composed of two coupled inductors, one bidirectional switch unit, and the dual-boost bridgeless power factor correction (PFC) rectifier. A bidirectional switch unit is embedded i...

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Veröffentlicht in:IEEE transactions on power electronics 2021-11, Vol.36 (11), p.12565-12578
Hauptverfasser: Ma, Hui, Zheng, Kaitong, Jiang, Hao, Yin, Hongpeng
Format: Artikel
Sprache:eng
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Zusammenfassung:In this article, a family of dual-boost bridgeless five-level rectifiers with common-core inductors is proposed, which is composed of two coupled inductors, one bidirectional switch unit, and the dual-boost bridgeless power factor correction (PFC) rectifier. A bidirectional switch unit is embedded in the midpoint between the two capacitors and the bridge arm of the dual-boost bridgeless PFC (DBBL-PFC) to directly generate the five-level waveforms in each line cycle. The proposed topologies have the characteristics of lower voltage/current stresses and low total harmonic distortion. Additionally, the proposed five-level rectifiers employ a pair of common-core coupled inductors at the input side to replace the inherent independent inductors to improve the core utilization and the power density. First, the characteristics of the proposed topologies are analyzed and compared, and one of the topologies is taken as an example to illustrate its operating principle. Second, the modulation strategy with strong topology applicability and control system is designed for the proposed topologies. The advantage of the proposed pulsewidth modulation method is that it only needs to change the pulse distribution of the five-level topology to realize the five-level rectification, and the program debugging is simple. Then, the coupled inductors are designed, compared, and analyzed by the equivalent model in detail. Finally, a rated output of 1 kW/400 V experimental prototype is built, and the experimental results are presented to demonstrate the performance and effectiveness of the proposed topologies.
ISSN:0885-8993
1941-0107
DOI:10.1109/TPEL.2021.3078533