SET Characterization and Mitigation in 65-nm CMOS Test Structures
SET propagation and mitigation in 65-nm CMOS test structures are investigated. Radiation tests showed a clear distortion of the SET pulse-widths related to the structures' design and layout as well as the efficacy of the employed mitigation techniques. Recommendations are provided to designers...
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| Veröffentlicht in: | IEEE transactions on nuclear science 2012-08, Vol.59 (4), p.851-859 |
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| container_title | IEEE transactions on nuclear science |
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| creator | Rezgui, Sana Won, Raymond Tien, Jonathan |
| description | SET propagation and mitigation in 65-nm CMOS test structures are investigated. Radiation tests showed a clear distortion of the SET pulse-widths related to the structures' design and layout as well as the efficacy of the employed mitigation techniques. Recommendations are provided to designers to simulate their designs to radiation effects, accounting for their layout and routing switches in the case of FPGAs. A special attention was also given to the trade-offs between charge sharing and charge collection efficiency of the first ion hits on a CMOS node that will greatly impact the final propagated SET pulse width in a given circuit layout. |
| doi_str_mv | 10.1109/TNS.2012.2196768 |
| format | Article |
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Radiation tests showed a clear distortion of the SET pulse-widths related to the structures' design and layout as well as the efficacy of the employed mitigation techniques. Recommendations are provided to designers to simulate their designs to radiation effects, accounting for their layout and routing switches in the case of FPGAs. A special attention was also given to the trade-offs between charge sharing and charge collection efficiency of the first ion hits on a CMOS node that will greatly impact the final propagated SET pulse width in a given circuit layout.</description><identifier>ISSN: 0018-9499</identifier><identifier>EISSN: 1558-1578</identifier><identifier>DOI: 10.1109/TNS.2012.2196768</identifier><identifier>CODEN: IETNAE</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Accounting ; Charge ; Charge sharing ; Circuits ; CMOS ; Delay ; Distortion ; Effectiveness ; fault injection ; Field programmable gate arrays ; Inverters ; Junctions ; Layout ; propagation and mitigation ; radiation tests ; reprogrammable and non-volatile flash-based FPGAs ; Routing ; SET characterization ; Switches ; Table lookup ; Tradeoffs</subject><ispartof>IEEE transactions on nuclear science, 2012-08, Vol.59 (4), p.851-859</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. 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Radiation tests showed a clear distortion of the SET pulse-widths related to the structures' design and layout as well as the efficacy of the employed mitigation techniques. Recommendations are provided to designers to simulate their designs to radiation effects, accounting for their layout and routing switches in the case of FPGAs. A special attention was also given to the trade-offs between charge sharing and charge collection efficiency of the first ion hits on a CMOS node that will greatly impact the final propagated SET pulse width in a given circuit layout.</description><subject>Accounting</subject><subject>Charge</subject><subject>Charge sharing</subject><subject>Circuits</subject><subject>CMOS</subject><subject>Delay</subject><subject>Distortion</subject><subject>Effectiveness</subject><subject>fault injection</subject><subject>Field programmable gate arrays</subject><subject>Inverters</subject><subject>Junctions</subject><subject>Layout</subject><subject>propagation and mitigation</subject><subject>radiation tests</subject><subject>reprogrammable and non-volatile flash-based FPGAs</subject><subject>Routing</subject><subject>SET characterization</subject><subject>Switches</subject><subject>Table lookup</subject><subject>Tradeoffs</subject><issn>0018-9499</issn><issn>1558-1578</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2012</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNpdkD1PwzAQhi0EEqWwI7FEYmFJ8fkr9lhF5UNq6ZAwW07qgKs2KXYywK_HVSoGptMrPe_d6UHoFvAMAKvH8q2YEQxkRkCJTMgzNAHOZQo8k-dogjHIVDGlLtFVCNsYGcd8gubFokzyT-NN3VvvfkzvujYx7SZZud59jNG1ieBpu0_y1bpIShv6pOj9UPeDt-EaXTRmF-zNaU7R-9OizF_S5fr5NZ8v05oq3KeC24ZVjEilqkYSyaWpgOFaMrmJRGZoxgjQDa0staAorlhWA8HKEMoYJ3SKHsa9B999DfEHvXehtrudaW03BA0UuJCKQxbR-3_otht8G7_TgCWBeJ3TSOGRqn0XgreNPni3N_47QvroVEen-uhUn5zGyt1YcdbaP1wQEEwQ-gtpp27R</recordid><startdate>20120801</startdate><enddate>20120801</enddate><creator>Rezgui, Sana</creator><creator>Won, Raymond</creator><creator>Tien, Jonathan</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. 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Radiation tests showed a clear distortion of the SET pulse-widths related to the structures' design and layout as well as the efficacy of the employed mitigation techniques. Recommendations are provided to designers to simulate their designs to radiation effects, accounting for their layout and routing switches in the case of FPGAs. A special attention was also given to the trade-offs between charge sharing and charge collection efficiency of the first ion hits on a CMOS node that will greatly impact the final propagated SET pulse width in a given circuit layout.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/TNS.2012.2196768</doi><tpages>9</tpages></addata></record> |
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| ispartof | IEEE transactions on nuclear science, 2012-08, Vol.59 (4), p.851-859 |
| issn | 0018-9499 1558-1578 |
| language | eng |
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| source | IEEE Electronic Library (IEL) |
| subjects | Accounting Charge Charge sharing Circuits CMOS Delay Distortion Effectiveness fault injection Field programmable gate arrays Inverters Junctions Layout propagation and mitigation radiation tests reprogrammable and non-volatile flash-based FPGAs Routing SET characterization Switches Table lookup Tradeoffs |
| title | SET Characterization and Mitigation in 65-nm CMOS Test Structures |
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