Layout-Aware Multi-Cell Upsets Effects Analysis on TMR Circuits Implemented on SRAM-Based FPGAs

Multiple Cell Upsets (MCUs) are becoming a growing concern with the advent of the newest FPGA devices. In this paper we present a methodology suitable for analyzing the sensitivity of circuits implemented in SRAM-based FPGAs, and adopting the TMR mitigation scheme. Data about the layout of the adopted FPGA are obtained by means of laser testing. Then static analysis algorithm uses the collected data to predict the impact of MCUs on designs implemented on SRAM-based FPGAs. Thanks to this approach MCUs affecting physically adjacent cells are considered, only. We report data focusing on a Virtex-II device, showing the capabilities of the proposed method.