An Analysis of Single Event Upset Dependencies on High Frequency and Architectural Implementations within Actel RTAX-S Family Field Programmable Gate Arrays

In order to investigate frequency and architectural effects on Single Event Upset cross sections within RTAX-S FPGA devices, a novel approach to high speed testing is implemented. Testing was performed at variable speeds ranging from 15 MHz to 150 MHz

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Bibliographische Detailangaben
Veröffentlicht in:	IEEE transactions on nuclear science 2006-12, Vol.53 (6), p.3569-3574
Hauptverfasser:	Berg, M., Jih-Jong Wang, Ladbury, R., Buchner, S., Hak Kim, Howard, J., LaBel, K., Phan, A., Irwin, T., Friendlich, M.
Format:	Artikel
Sprache:	eng
Schlagworte:	Actel anti-fuse Clocks Cross sections Devices Field programmable gate arrays FPGA Frequency High frequencies high frequency High speed Logic devices NASA Pulse inverters Shift registers Single event upset Single event upsets Space technology Testing TMR transients Variable speed
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Beschreibung
Zusammenfassung:	In order to investigate frequency and architectural effects on Single Event Upset cross sections within RTAX-S FPGA devices, a novel approach to high speed testing is implemented. Testing was performed at variable speeds ranging from 15 MHz to 150 MHz
ISSN:	0018-9499 1558-1578
DOI:	10.1109/TNS.2006.886043