A Low-Cost FPGA-Based Coarse-Fine Counting Time-to-Digital Converter With External High-Precision Reference Clock

A new coarse-fine counter time-to-digital converter (TDC) architecture and its implementation techniques for high-precision time-interval measurement are presented. Multicoarse counters and one fine counter are combined in our TDC architecture. The calibration circuit employs a START and STOP calibration signal generator and a gain calibration circuit. Arbitrarily small time intervals can be measured by distributing the START and STOP signals on different channels. In the implementation process, the high-precision external clock produced by a Silicon Si5338 EVB board and the on-chip high-precision clock are combined to calibrate the TDC output data in real-time. The TDC is implemented on a specially designed field-programmable gate array (FPGA) board with a low-cost Xilinx Artix-7 35T FPGA. The measured least significant bit (LSB) is 17.9 ps and the calculated peak-to-peak differential nonlinearity (DNL) and integral nonlinearity (INL) values are 1.006 and 0.920 LSB. The root-mean-square (rms) resolution is lower than 20 ps in continuous measurement.