Improved Blind Timing Skew Estimation Based on Spectrum Sparsity and ApFFT in Time-Interleaved ADCs

Timing skews among channels degrade seriously the time-interleaved analog-to-digital converter (TIADC) performance, which can be improved by the blind timing skew estimation (TSE) technique. In this paper, we proposed the all-phase fast Fourier transform (ApFFT) based on spectrum sparsity signal phase relationship blind TSE (ApFFT-SSPR-BLTSE) algorithm. The ApFFT-SSPR-BLTSE algorithm reduces computational complexity based on the phase relationship of the total output from TIADC and the corresponding reference channel output compared with the existing spectrum sparsity blind TSE (SS-BLTSE) algorithm. We also utilized the ApFFT technique to increase the accuracy of phase spectral estimation. Simulation results show that the proposed ApFFT-SSPR-BLTSE algorithm, which as a reduced number of fast Fourier transforms (FFTs) and low hardware complexity, has higher accuracy for blind TSE compared to the existing SS-BLTSE algorithm. In addition, this paper presents an efficient hardware architecture of the ApFFT-SSPR-BLTSE algorithm on the Xilinx Virtex-6 vlx550tff1759 field-programmable gate array (FPGA) chip for the blind TSE of the four-channel 400-MHz 14-bit TIADC real system. The validation results show that the proposed algorithm uses only a few percent of the hardware resources of the FPGA chip, and the mismatch spurs were suppressed to better than −81.54 dB.