Novel Method to Measure the Capacitive Matching of A/D Converter Based on Successive Approximation

Analog-to-digital converters (ADCs) based on successive approximation are widely used in many applications. Systems with price pressure such as electrical motor drives often use lower resolution 12-bit ADCs instead of the 16-bit high grades, as the price increases exponentially with the resolution. This is caused by the essential test costs. Production test times with up to 60 s are common. Reducing the test time is therefore an essential area of research and would enable affordable end products with higher accuracy. Optimizations such as real time histogramming reduced the production test already to 24 s. Now, the limiting factors are the calibration process (trimming) and the linearity test. This paper presents a novel idea to reduce the trim time by a factor of 20 without the loss of accuracy. The method was implemented on silicon. Measurement results are presented.