Dynamically Reconfigurable Architecture Design for Ultrasonic Imaging

Ultrasonic imaging algorithms, including detection and compression, are computationally complex and difficult to implement in hardware for real-time applications. In this paper, we present an ultrasonic reconfigurable subband decomposition processor (RSDP) that can employ wavelet filters for frequen...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Veröffentlicht in:IEEE transactions on instrumentation and measurement 2009-08, Vol.58 (8), p.2856-2866
Hauptverfasser: Oruklu, E., Saniie, J.
Format: Artikel
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:Ultrasonic imaging algorithms, including detection and compression, are computationally complex and difficult to implement in hardware for real-time applications. In this paper, we present an ultrasonic reconfigurable subband decomposition processor (RSDP) that can employ wavelet filters for frequency diverse signal processing. This architecture enables parallel implementation of a lifting-based discrete wavelet transform. The configurability of the architecture applies to the selection of wavelet kernels and scales for subband decomposition, thresholding operation for compression, and the postprocessing detection algorithm. The underlying hardware design makes use of the fact that both compression and detection applications share the same algorithm fundamentals. A unified architecture has been designed that implements signal decomposition and reconstruction with forward and inverse discrete wavelet transforms. After the forward transform step, a windowing operation is applied to discriminate frequency bands for target detection. Using the same architecture, a thresholding operation is applied to wavelet coefficients for data compression. The flexibility and the modular design make this reconfigurable architecture an effective and practical solution for real-time ultrasonic imaging applications. The resulting architecture is adaptable, fast, and suitable for a system-on-a-chip implementation that requires minimal logic resources.
ISSN:0018-9456
1557-9662
DOI:10.1109/TIM.2009.2016370