A Robust Algorithm to Identify the Test Stimulus in Histogram-Based A/D Converter Testing

Traditional testing of analog-to-digital converters (ADCs) with automatic test equipment is time-consuming and expensive, and a built-in self-test (BIST) can be one solution to this problem. Most of the proposed BIST routines require a well-known test stimulus which is much more linear than the device under test. A stimulus error identification and removal (SEIR) method that does not require a high-linearity stimulus has been proposed recently, and it is evident that reliable test results could be achieved with a stimulus linearity lower than the required measurement accuracy. This paper presents a simple and easy-to-implement calculation algorithm for use with the stimulus-identification method, particularly for BIST purposes. Simulations demonstrate that the integral-nonlinearity measuring accuracy of the SEIR method with the new calculation algorithm is 1 least significant bit for 14-b ADCs, even though the linearity of the test stimulus is only 7 b. The SEIR method and the new simpler calculation algorithm can reduce the hardware resources required for ADC BIST.