Suppression of Dynamic Resistance Degradation in 1200-V GaN-on-Sapphire E-Mode GaN HEMTs by Drain-Side Thin p-GaN Design

Dynamic resistance degradation, which is severely affected by the trapping effect, is a critical challenge for lateral AlGaN/GaN power devices, especially when operating in high-voltage and high-frequency applications. In this brief, an enhancement-mode p-GaN gate HEMT with a drain-side thin p-GaN (...

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Veröffentlicht in:	IEEE transactions on electron devices 2025-02, p.1-4
Hauptverfasser:	Wang, Wenfeng, Zhou, Feng, Qian, Junfan, Zou, Can, Xu, Weizong, Ren, Fangfang, Zhou, Dong, Chen, Dunjun, Xia, Yuanyang, Wu, Leke, Li, Yiheng, Zhu, Tinggang, Zheng, Youdou, Zhang, Rong, Lu, Hai
Format:	Artikel
Sprache:	eng
Schlagworte:	1200-V OFF-state bias stress Degradation drain-side p-GaN dynamic resistance degradation GaN-on-sapphire HEMTs High-voltage techniques Logic gates MODFETs Ohmic contacts p-GaN HEMT Performance evaluation Stress Switching circuits Wide band gap semiconductors
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