Analysis Method of Dynamic Read Variation in a TFT-Type Synaptic Devices With Poly-Si Channel Structure

A novel method of analyzing the dynamic read variation (equivalent gate bias deviation [ \delta ( {V}_{\text {G}} )] over a wide gate-voltage range of devices is proposed and applied to CMOS-compatible TFT-type synaptic devices with poly-Si channel. Since the proposed method of current sampling in a time domain or DC sweep shows a similar trend of \delta ( {V}_{\text {G}} ) for any FET-like devices, read variation can be estimated simply with greatly reduced measurement time. In addition, the proposed method can be utilized to analyze the reliability characteristics of FET-like devices, which is a promising solution to the current need for innovative analysis methods required as the devices become smaller. Considering dynamic variations of the fabricated synaptic device, the quantized VGG9 network for CIFAR-10 image classification simulation shows a