Understanding Retention Time Distribution in Buried-Channel-Array-Transistors (BCAT) Under Sub-20-nm DRAM Node-Part I: Defect-Based Statistical Compact Model

In Part I of this article, the static leakage-induced retention time distribution in buried-channel-array-transistors (BCATs) within sub-20-nm dynamic random access memory (DRAM) cells is investigated. By separating the leakage into nontrap and trap-induced components, we explored the physical mechanisms behind it. A defect-based statistical compact leakage model is developed by incorporating factors, such as defect density, spatial location, and the distribution of energy levels. We show that this defect-based statistical model helps elucidate the relationship between inherent defects and the retention time characteristics of DRAM. Furthermore, its compact nature makes it possible to investigate the retention time distribution at higher sigma levels in-depth. By linking the defect directly to the retention time, the proposed model lays the foundation for positive bias temperature instability (PBTI) aging analysis and process optimization reported in Part II of this article.