High-Density Embedded 3-D Stackable Via RRAM in 16-nm FinFET CMOS Logic Process

This study introduces a breakthrough achievement of 0.1-Gb/mm2 wing-shaped high-density embedded 3-D via resistive random access memory (Via RRAM) in TSMC's 16-nm FinFET CMOS logic process. The 3-D Via RRAM cell is vertically structured as a 1T10R configuration; these ten switchable resistive unit cells stacked across five copper layers. Notably, it seamlessly integrates with standard FinFET CMOS logic processes without additional masking or process steps. Also, the set/reset operations and the resistance distributions are analyzed. Importantly, the 3-D Via RRAM shows good scalability and adaptability in more metal layers and advanced structure of new technologies, such as GAA and complementary FET (CFET). Summarily, the innovative CMOS logic-compatible 3-D Via RRAM is developed for system on a chip (SoC), high-performance microcontroller units (MCUs), and advanced embedded CMOS logic applications.