Optimization and Benchmarking FinFETs and GAA Nanosheet Architectures at 3-nm Technology Node: Impact of Unique Boosters

Using a full design-technology cooptimization (DTCO) framework, we benchmark gate-all-around (GAA) nanosheet (NS) FETs against FinFETs at 3-nm logic technology relevant dimensions. First, to understand the intrinsic gain from NS, both device architectures are simulated using fixed technology ground rules [contact poly pitch (CPP), metal pitch {M}_{x} , and cell height] and process assumptions (PAs), including stress, doping, junctions, and oxide thickness. Full geometry optimization along the CPP direction (gate length {L}_{\text {G}} , spacer thickness {T}_{\text {SP}} , and contact length {L}_{\text {CNT}} ) is done to self-consistently account for tradeoff between short-channel effects (SCE), intrinsic and extrinsic resistances, and capacitances (device and parasitic). This leads to independent optimum design specifications for each Fin and NS architectures. Impact of Fin tapering and NS width and stack number are further investigated, showing additional design flexibility of GAA NS devices at scaled dimensions.