An Analytical Model of Hot Carrier Degradation in LDMOS Transistors: Rediscovery of Universal Scaling

It is well-known that regardless of the voltage/temperature/device structure, the hot carrier degradation (HCD) of classical logic transistors scales onto a single universal curve, offering a theory-agnostic approach to predict long-term degradation based on short-term accelerated tests. Based on the experimental results, it has been suggested that the HCD in power transistors [e.g., laterally diffused MOS (LDMOS)] is structurally and functionally so fundamentally different that an analogous universal scaling cannot apply. This article uses a tandem FET (two MOS) model of an LDMOS to explore the physical origin of the anomalous HCD degradation in power transistors and establish the general principle needed to restore the universality of the degradation kinetics. Interestingly, the empirical models used to evaluate HCD degradation in power transistors emerge naturally as approximations of the generalized approach. This article establishes the fact that the physics of HCD is universal and provides an example of nonclassical but predictive degradation in power transistors. This takes us a step closer to a generalized HCD model encompassing all the devices, including logic, memory, and power transistors.